Leonard P. GULER
62Patents
3h-index
92Co-inventors
65Inventor score
Filing activity: Sep 25, 2013 → Apr 2, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11233152B2 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | Electricity | 5 | Active |
| US11855223B2 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | Electricity | 5 | Active |
| US11342411B2 | Cavity spacer for nanowire transistors | Electricity | 4 | Active |
| US10559529B2 | Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication and structures resulting therefrom | Electricity | 3 | Active |
| US10522402B2 | Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects and structures resulting therefrom | Electricity | 3 | Active |
| US12002810B2 | Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach | Electricity | 2 | Active |
| US11302790B2 | Fin shaping using templates and integrated circuit structures resulting therefrom | Electricity | 2 | Active |
| US10541143B2 | Self-aligned build-up of topographic features | Electricity | 2 | Active |
| US11404578B2 | Dielectric isolation layer between a nanowire transistor and a substrate | Electricity | 2 | Active |
| US11043492B2 | Self-aligned gate edge trigate and finFET devices | Electricity | 1 | Active |
| US11929396B2 | Cavity spacer for nanowire transistors | Electricity | 1 | Active |
| US11398474B2 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Electricity | 1 | Active |
| US12328905B2 | Cavity spacer for nanowire transistors | Electricity | 0 | Active |
| US12408422B2 | Integrated circuit structures with backside gate cut or trench contact cut | Electricity | 0 | Active |
| US12342612B2 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Electricity | 0 | Active |
| US12249541B2 | Vertical edge blocking (VEB) technique for increasing patterning process margin | Electricity | 0 | Active |
| US11715775B2 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures | Electricity | 0 | Active |
| US12068314B2 | Fabrication of gate-all-around integrated circuit structures having adjacent island structures | Electricity | 0 | Active |
| US12224350B2 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | Electricity | 0 | Active |
| US12057491B2 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates | Electricity | 0 | Active |
| US11569370B2 | DEPOP using cyclic selective spacer etch | Electricity | 0 | Active |
| US12349394B2 | Dielectric isolation layer between a nanowire transistor and a substrate | Electricity | 0 | Active |
| US11355608B2 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures | Electricity | 0 | Active |
| US12419085B2 | Integrated circuit structures having backside gate tie-down | Electricity | 0 | Active |
| US12014959B2 | Integrated nanowire and nanoribbon patterning in transistor manufacture | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.