Packages with Si-substrate-free interposer and method forming same
US10522449B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2017 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Jul 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4694
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.