Memory device and method for manufacturing same
US10522460B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2017 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Dec 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first conductive layer; a second conductive layer provided above the first conductive layer; a plurality of electrode layers stacked above the second conductive layer; a semiconductor pillar extending through the plurality of electrode layers and the second conductive layer, and connected to the first conductive layer; and a third conductive layer provided above the first conductive layer. The third conductive layer is positioned at a level substantially same as a level of the second conductive layer in an extension direction of the semiconductor pillar, and is made of a material same as a material of the second conductive layer. The third conductive layer is electrically isolated from the second conductive layer, and is electrically connected to the first conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.