Semiconductor chip, and fabrication and packaging methods thereof

US10522479B2 · kind B2 · utility

Assignees

• Semiconductor Manufacturing International (Shanghai) Corporation · CN
• Semiconductor Manufacturing International (Beijing) Corporation · CN

Inventors

• Li Hui Lu · Shanghai, CN
• Chun Chao Fei · Shanghai, CN
• Po Yuan Chiang · Shanghai, CN
• Ya Ping Wang · Shanghai, CN

Key dates

• Filing date: May 21, 2018
• Grant date: Dec 31, 2019
• Expiry date: May 21, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/35121
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for fabricating a semiconductor structure includes forming a semiconductor chip. Forming the semiconductor chip includes providing a substrate, forming a connection layer on the substrate, and forming a first passivation layer on the substrate. The first passivation layer contains a plurality of first openings to expose the connection layer. Forming the semiconductor chip also includes forming a plurality of second openings and a plurality of third openings in the second passivation layer. Each second opening is formed in a first opening to expose the connection layer, and each third opening is formed outside of the plurality of first openings to expose the first passivation layer. Further, forming the semiconductor chip includes forming a conductive bump in each second opening.