Uniform gate dielectric for DRAM device
US10522549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Apr 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26506
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.