Surface topography by forming spacer-like components
US10522557B2 · kind B2 · utility
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49References
20Claims
0Family size
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Key dates
| Filing date | Oct 30, 2017 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Oct 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.