Semiconductor package with embedded capacitor and methods of manufacturing same
US10522615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2016 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Oct 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.