Sergio A. Ajuria
13Patents
8h-index
21Co-inventors
72Inventor score
Filing activity: Jun 2, 1993 → Dec 7, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5324683A | Method of forming a semiconductor structure having an air region | Emerging Cross-Sectional Technologies | 505 | Expired |
| US5510645A | Semiconductor structure having an air region and method of forming the semiconductor structure | Emerging Cross-Sectional Technologies | 162 | Expired |
| US5736435A | Process for fabricating a fully self-aligned soi mosfet | Electricity | 105 | Expired |
| US5837612A | Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation | Emerging Cross-Sectional Technologies | 98 | Expired |
| US5885870A | Method for forming a semiconductor device having a nitrided oxide dielectric layer | Electricity | 89 | Expired |
| US5963818A | Combined trench isolation and inlaid process for integrated circuit formation | Electricity | 41 | Expired |
| US5665620A | Method for forming concurrent top oxides using reoxidized silicon in an EPROM | Electricity | 14 | Expired |
| US9548266B2 | Semiconductor package with embedded capacitor and methods of manufacturing same | Electricity | 13 | Active |
| US9601354B2 | Semiconductor manufacturing for forming bond pads and seal rings | Electricity | 2 | Active |
| US10522615B2 | Semiconductor package with embedded capacitor and methods of manufacturing same | Electricity | 1 | Active |
| US10553508B2 | Semiconductor manufacturing using disposable test circuitry within scribe lanes | Electricity | 1 | Active |
| US9134366B2 | Method for forming a packaged semiconductor device | Electricity | 0 | Active |
| US8059380B2 | Package level ESD protection and method therefor | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.