Multi-gate semiconductor device and method for forming the same
US10522622B2 · kind B2 · utility
3Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | May 14, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | May 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.