Chao-Ching Cheng
123Patents
7h-index
56Co-inventors
73Inventor score
Filing activity: Nov 18, 2011 → Jul 4, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10134640B1 | Semiconductor device structure with semiconductor wire | Electricity | 21 | Active |
| US10714592B2 | Method of manufacturing a semiconductor device and a semiconductor device | Electricity | 11 | Active |
| US10355102B2 | Semiconductor device and method of manufacturing the same | Electricity | 11 | Active |
| US10374059B2 | Structure and formation method of semiconductor device structure with nanowires | Electricity | 9 | Active |
| US10297508B2 | Semiconductor device and method | Electricity | 9 | Active |
| US10403550B2 | Method of manufacturing a semiconductor device and a semiconductor device | Electricity | 8 | Active |
| US11038044B2 | Semiconductor device and manufacturing method thereof | Electricity | 7 | Active |
| US10636891B2 | Method of manufacturing a semiconductor device and a semiconductor device | Electricity | 7 | Active |
| US10672667B2 | Semiconductor device and method | Electricity | 6 | Active |
| US10062782B2 | Method of manufacturing a semiconductor device with multilayered channel structure | Electricity | 5 | Active |
| US11038043B2 | Semiconductor device and manufacturing method thereof | Electricity | 5 | Active |
| US10361278B2 | Method of manufacturing a semiconductor device and a semiconductor device | Electricity | 5 | Active |
| US11145676B1 | Memory device and multi-level memory cell having ferroelectric storage element and magneto-resistive storage element | Electricity | 4 | Active |
| US11004965B2 | Forming semiconductor structures with two-dimensional materials | Electricity | 4 | Active |
| US10991811B2 | Structure and formation method of semiconductor device structure with nanowires | Electricity | 3 | Active |
| US10818777B2 | Method of manufacturing a semiconductor device and a semiconductor device | Electricity | 3 | Active |
| US10930795B2 | Nanowire stack GAA device with inner spacer and methods for producing the same | Electricity | 3 | Active |
| US10886182B2 | Method of manufacturing a semiconductor device and a semiconductor device | Electricity | 3 | Active |
| US10868114B2 | Isolation structures of semiconductor devices | Electricity | 3 | Active |
| US10930498B2 | Methods for producing nanowire stack GAA device with inner spacer | Electricity | 3 | Active |
| US11056400B2 | Semiconductor device and method | Electricity | 3 | Active |
| US10522622B2 | Multi-gate semiconductor device and method for forming the same | Electricity | 3 | Active |
| US8878302B2 | Semiconductor device having SiGe substrate, interfacial layer and high K dielectric layer | Electricity | 3 | Active |
| US9406518B2 | (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate | Electricity | 2 | Active |
| US10651314B2 | Nanowire stack GAA device with inner spacer and methods for producing the same | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.