V-grooved vertical channel-type 3D semiconductor memory device and method for manufacturing the same
US10522624B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 28, 2017 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Nov 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/823
Abstract
A method of fabricating a vertical channel 3D semiconductor memory device is disclosed. In one aspect, the method comprises providing a stack of alternating layers of conductive material and dielectric material on a major surface of substrate, providing in the stack at least one trench, having sloped sidewalls sloping towards the major surface, extending at least below the lowest layer of conductive material, forming, in order, a programmable material, a channel liner, and a filler material on the sidewalls of the trench. Thereby, the method forms a memory string, and an electrode to the channel liner at opposite ends of the memory string.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.