Integrated JFET structure with implanted backgate
US10522663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Aug 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.