Techniques for MRAM MTJ top electrode to metal layer interface including spacer
US10522740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | May 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in contact with the upper metal layer. A sidewall spacer surrounds an outer periphery of the top electrode. An etch stop layer is disposed on top of an outer periphery of the spacer top surface and surrounding an outer periphery of the bottom surface of the upper metal layer. The etch stop layer overhangs the outer periphery of the spacer top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.