CMOS inverters with asymmetric contact distances and methods of making such inverters
US10523206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Apr 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein includes forming a first transistor for an inverter and forming asymmetrically spaced first and second conductive contact structures that are conductively coupled to the source region and the drain region, respectively, of the transistor. In this example, the first conductive contact structure (for the source region) is positioned a first predetermined target distance from a first side of the gate structure of the transistor, and the second conductive contact structure (for the drain region) is positioned a second predetermined target distance from a second side of the gate structure, wherein the second predetermined target distance is less than the first predetermined target distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.