Test circuitry and techniques for logic tiles of FPGA
US10523209B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Nov 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit comprising a plurality of logic tiles, wherein, during operation, each logic tile is configurable to connect with at least one other logic tile, and wherein each logic tile includes: (1) a normal operating mode, (2) a test mode, (3) an interconnect network including a plurality of multiplexers, wherein during operation, the interconnect network of each logic tile is configurable to electrically connect with the interconnect network of at least one adjacent logic tile of the plurality of logic tiles via one or more tile-to-tile interconnects in the normal operating mode and (4) isolation circuitry, connected between the associated interconnect network and the interconnect network of each adjacent logic tile, configurable to responsively disconnect tile-to-tile interconnects disposed between the interconnect network of each adjacent logic tile in the test mode to thereby electrically disconnect interconnect networks of adjacent logic tiles in the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.