LIN-compatible fast-data bus
US10523461B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 11, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Jun 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/40273
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods and transceivers are provided for enabling fast-data messages on a local interconnect network (LIN) compatible bus. One illustrative slave transceiver embodiment includes: a comparator and a digital-to-analog converter (DAC). The comparator detects amplitude modulation of a bias voltage at a first baud rate on a serial bus line to receive a first LIN frame header having a frame identifier for a fast-data frame. The DAC responsively drives a fast-data response message having an expanded payload and/or a higher baud rate on the serial bus line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.