Clock retiming circuit
US10528076B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2017 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Sep 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock retiming circuit and method of operating a clock retiming circuit are described herein. A clock retiming circuit generates a retimed clock based on an input clock. The clock retiming circuit may have a normal mode when the input clock is available to the clock retiming circuit, and a retention mode that is entered in response to the input clock no longer being present. The clock retiming circuit resumes the normal mode in response to the clock again being present. The retention mode is a low current mode, in one aspect. Thus, the clock retiming circuit may operate in a low current mode when the input clock is not available. The clock retiming circuit may be tolerant to loss of the input clock. The clock retiming circuit may quickly re-establish the retimed clock in response to the input clock again becoming available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.