Fast detection of defective memory block to prevent neighbor plane disturb
US10529435B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2018 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Jan 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.