Patent · US Active

Electronic power devices integrated with an engineered substrate

US10529613B2 · kind B2 · utility

1Cited by

1References

7Claims

0Family size

Assignee

Qromis, Inc. · US

Inventors

Vladimir Odnoblyudov · Danville, US
Dilip Risbud · San Jose, US
Ozgur Aktas · Santa Clara, US
Cem Basceri · Boise, US

Key dates

Filing date	Jul 1, 2019
Grant date	Jan 7, 2020
Priority date	—
Expiry date	Jul 1, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/111
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.