3D stacked dies with disparate interconnect footprints
US10529693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2017 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Nov 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a front side and a back side and plural through chip vias. The through chip vias have a first footprint. The back side is configured to have a second semiconductor chip stacked thereon. The second semiconductor chip includes plural interconnects that have a second footprint larger than the first footprint. The back side includes a backside interconnect structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.