Methods and systems for wafer bonding alignment compensation
US10529694B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2018 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Jul 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of methods and systems for wafer bonding alignment compensation are disclosed. The method comprises bonding a first pair of wafers including multiple bonding alignment mark pairs on the first pair of wafers; first analyzing a translational misalignment and a rotational misalignment between the first pair of wafers based on a measurement of at least two bonding alignment mark pairs; controlling a wafer position adjustment module to compensate for the translational misalignment and the rotational misalignment during bonding of a second pair of wafers based on the first analysis; second analyzing a mean run-out misalignment between the first pair of wafers based on a measurement of the multiple bonding alignment mark pairs; and controlling a wafer deformation adjustment module to compensate for the run-out misalignment during bonding of a third pair of wafers based on the second analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.