Methods and apparatus for a dynamic addressing decimation filter
US10530340B1 · kind B1 · utility
0Cited by
5References
20Claims
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Assignee
Inventor
Key dates
| Filing date | Dec 26, 2018 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Dec 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/462
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present technology may comprise a method, apparatus or system for dynamic addressing decimation filtering. In various embodiments, the apparatus comprises an analog modulator and a multi-bit dynamically addressing decimation filter. By pairing an analog modulator with the proper configuration with a multi-bit dynamically addressing decimation filter with the proper matching number of physical sub decimation filters, decimation filtering can be completed with a smaller number of physical sub decimation filters “N” than the quantizer level “M.”
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.