Packaging structure of a microelectronic device having a hermeticity improved by a diffusion barrier layer

US10532924B2 · kind B2 · utility

Assignees

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR
• EPCOS AG · DE

Inventors

• Damien Saint-Patrice · Valence, FR
• Arnoldus Den Dekker · Beuningen, NL
• Marcel Giesen · Munich, DE
• Gudrun Henn · Ebenhausen, DE
• Jean-Louis Pornin · Crolles, FR
• Bruno Reig · Moirans, FR

Key dates

• Filing date: Dec 6, 2013
• Grant date: Jan 14, 2020
• Expiry date: Dec 6, 2033

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B81C2203/0145
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A packaging structure including at least one hermetically sealed cavity in which at least one microelectronic device is arranged, the cavity being formed between a substrate and at least one cap layer through which several release holes are formed. Several separated portions of metallic material are provided such that each of the separated portions of metallic material is arranged on the cap layer above and around one of the release holes and forms an individual and hermetical plug of said one of the release holes. At least one diffusion barrier layer including at least one non-metallic material is arranged on the cap layer and forms a diffusion barrier against an atmosphere outside the cavity at least around the release holes. Parts of the diffusion barrier layer are not covered by the portions of metallic material.