Method of applying vertex based corrections to a semiconductor design
US10534255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2015 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Feb 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of geometry corrections to properly transfer semiconductor designs on a wafer or a mask in nanometer scale processes is provided. In contrast with some prior art techniques, geometry corrections and possibly dose corrections are applied before fracturing. Unlike edge based corrections, where the edges are displaced in parallel, the displacements applied to generated geometry corrections do not preserve parallelism of the edges, which is specifically well suited for free form designs. A seed design is generated from the target design. Vertices connecting segments are placed along the seed design contour. Correction sites are placed on the segments. Displacement vectors are applied to the vertices. A simulated contour is generated and compared to the contour of the target design. The process is iterated until a match criteria between simulated and target design (or another stop criteria) is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.