Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories
US10534394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Sep 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent mad commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.