Rescheduling threads using different cores in a multithreaded microprocessor having a shared register pool
US10534614B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2012 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | May 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a microprocessor in a first microprocessor thread requires a first logical register. Next a determination is made that a second instruction to be executed by the microprocessor in a second microprocessor thread requires a second logical register. A first physical register in the shared register pool is allocated to the first microprocessor thread for execution of the first instruction and the first logical register is mapped to the first physical register. A second physical register in the shared register pool is allocated to the second microprocessor thread for execution of the second instruction. Finally, the second logical register is mapped to the second physical register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.