Operation of a multi-slice processor implementing a unified page walk cache
US10534715B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Apr 22, 2016 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Sep 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more page walk caches, where operation includes: receiving, at a load/store slice, an instruction to be issued; determining, at the load/store slice, a process type indicating a source of the instruction to be a host process or a guest process; and determining, in accordance with an allocation policy and in dependence upon the process type, an allocation of an entry of the page walk cache, wherein the page walk cache comprises one or more entries for both host processes and guest processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.