Method of debugging a processor
US10534881B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 10, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Jul 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for designing a processor based on executing a randomly created and randomly executed executable on a fabricated processor. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that specific feature. This allows for the detection and diagnosis of errors and bugs in the processor that elude traditional testing methods. Once the errors and bugs are detected and diagnosed, the processor can then be redesigned to no longer produce the anomalies. By eliminating the errors and bugs in the processor, a processor with improved computational efficiency and reliability can be fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.