Determining ECO aggressor nets during incremental extraction
US10534889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2016 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Sep 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of extracting parasitics associated with a circuit design layout generated by modifying a previous iteration of the layout, includes, in part, identifying a first multitude of nets that have been changed in the circuit design layout relative to the previous iteration of the circuit design layout. The method further includes, in part, calculating a first multitude of parasitic capacitance values between each of the first multitude of first nets and each of a second multitude of nets disposed in proximity of the first multitude of nets. The method further includes, in part, identifying each net in the second multitude of nets as an aggressor net if a number defined by the net's associated parasitic capacitance value is higher than a threshold value. The method further includes excluding nets in the second multitude of second nets that are not identified as aggressor nets from the parasitic extraction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.