Dynamic bit-scan techniques for memory device programming
US10535401B2 · kind B2 · utility
5Cited by
3References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 5, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Jun 5, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.