Patent · US Active

Methods of forming a vertical semiconductor diode using an engineered substrate

US10535547B2 · kind B2 · utility

5Cited by

0References

10Claims

0Family size

Assignee

Qromis, Inc. · US

Inventors

Vladimir Odnoblyudov · Danville, US
Dilip Risbud · San Jose, US
Ozgur Aktas · Santa Clara, US
Cem Basceri · Boise, US

Key dates

Filing date	Dec 7, 2018
Grant date	Jan 14, 2020
Priority date	—
Expiry date	Dec 7, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/111
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.