Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate
US10535608B1 · kind B1 · utility
48Cited by
13References
19Claims
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Key dates
| Filing date | Jul 24, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Jul 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.