Three-dimensional memory devices and fabricating methods thereof
US10535669B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Oct 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of 3D memory structures and methods for forming the same are disclosed. A method for forming a three-dimensional (3D) memory structure includes forming a dielectric layer on a substrate and forming a first plurality of openings in the dielectric layer at a staircase region of the 3D memory structure. The method also includes forming a second plurality of openings in the dielectric layer at a peripheral device region of the 3D memory structure and forming at least one hard mask layer in the first plurality of openings of the staircase region and in the second plurality of openings of the peripheral device region. The method further includes etching the dielectric layer using the at least one hard mask layer to form first and second pluralities of via extension regions in top portions of the respective first and second pluralities of openings. The method further includes disposing a first conductive material in the first and second pluralities of openings to form respective first and second pluralities of contact wires. The method also includes disposing a second conductive material in the first and second pluralities of via extension regions to form first and second plur…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.