Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices
US10535752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | May 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.