Yi-Huan Chen
52Patents
4h-index
34Co-inventors
58Inventor score
Filing activity: Feb 5, 2016 → May 21, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10050033B1 | High voltage integration for HKMG technology | Electricity | 13 | Active |
| US10340357B2 | Dishing prevention dummy structures for semiconductor devices | Electricity | 7 | Active |
| US9831340B2 | Semiconductor structure and associated fabricating method | Electricity | 5 | Active |
| US10748899B2 | Epitaxial source and drain structures for high voltage devices | Electricity | 4 | Active |
| US11677022B2 | Semiconductor structure and method of forming thereof | Electricity | 2 | Active |
| US10553583B2 | Boundary region for high-k-metal-gate(HKMG) integration technology | Electricity | 2 | Active |
| US10516029B2 | Dishing prevention dummy structures for semiconductor devices | Electricity | 2 | Active |
| US10177043B1 | Method for manufacturing multi-voltage devices using high-K-metal-gate (HKMG) technology | Electricity | 2 | Active |
| US10510750B2 | High voltage integration for HKMG technology | Electricity | 1 | Active |
| US9853149B1 | Floating grid and crown-shaping poly for improving ILD CMP dishing | Electricity | 1 | Active |
| US11004844B2 | Recessed STI as the gate dielectric of HV device | Electricity | 1 | Active |
| US11302691B2 | High voltage integration for HKMG technology | Electricity | 1 | Active |
| US10535752B2 | Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices | Electricity | 1 | Active |
| US10790279B2 | High voltage integration for HKMG technology | Electricity | 1 | Active |
| US10916542B2 | Recessed STI as the gate dielectric of HV device | Electricity | 1 | Active |
| US10937785B2 | Semiconductor device | Electricity | 1 | Active |
| US12021140B2 | Semiconductor structure and method of forming thereof | Electricity | 1 | Active |
| US11527531B2 | Recessed gate for an MV device | Electricity | 1 | Active |
| US12414361B2 | Method of manufacturing a semiconductor device | Electricity | 0 | Active |
| US12211926B2 | Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices | Electricity | 0 | Active |
| US11569363B2 | Dishing prevention dummy structures for semiconductor devices | Electricity | 0 | Active |
| US11417649B2 | Semiconductor device | Electricity | 0 | Active |
| US11810973B2 | Semiconductor structure and method of forming thereof | Electricity | 0 | Active |
| US11855091B2 | Boundary design for high-voltage integration on HKMG technology | Electricity | 0 | Active |
| US10325964B2 | OLED merged spacer device | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.