Via structure, MRAM device using the via structure and method for fabricating the MRAM device
US10535816B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Aug 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
A via structure, a MRAM device using the via structure and a method for fabricating the MRAM device are provided. In the method for fabricating the MRAM device, at first, a first dielectric layer is deposited over a transistor. Then, a contact is formed in the first dielectric layer and electrically connected to the transistor. Thereafter, a metal nitride layer is deposited over the first dielectric layer and the contact. Then, an etch stop layer is deposited over the metal nitride layer. Thereafter, a second dielectric layer is deposited over the etch stop layer. Then, a via structure is formed in the second dielectric layer, the etch stop layer, and the metal nitride layer and landing on the contact. Thereafter, a memory stack is formed over the via structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.