Inventor · Guoxing Township, TW

Shing-Chyang Pan

54Patents
8h-index
65Co-inventors
81Inventor score

Filing activity: Jun 20, 2002 → Aug 3, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8361900B2 Barrier layer for copper interconnect Electricity 33 Active
US7193327B2 Barrier structure for semiconductor devices Electricity 30 Expired
US6656832B1 Plasma treatment method for fabricating microelectronic fabrication having formed therein conductor layer with enhanced electrical properties Electricity 20 Expired
US6846756B2 Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers Electricity 19 Expired
US6821905B2 Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer Electricity 16 Expired
US7704886B2 Multi-step Cu seed layer formation for improving sidewall coverage Electricity 12 Active
US9659811B1 Manufacturing method of semiconductor device Electricity 10 Active
US9679804B1 Multi-patterning to form vias with straight profiles Electricity 10 Active
US10685873B2 Etch stop layer for semiconductor devices Electricity 8 Active
US7253501B2 High performance metallization cap layer Electricity 8 Expired
US10978301B2 Morphology of resist mask prior to etching Electricity 5 Active
US7030023B2 Method for simultaneous degas and baking in copper damascene process Electricity 4 Expired
US10468297B1 Metal-based etch-stop layer Electricity 4 Active
US10535816B2 Via structure, MRAM device using the via structure and method for fabricating the MRAM device Electricity 4 Active
US7247252B2 Method of avoiding plasma arcing during RIE etching Electricity 4 Expired
US7805258B2 System and method for film stress and curvature gradient mapping for screening problematic wafers Electricity 3 Active
US8252690B2 In situ Cu seed layer formation for improving sidewall coverage Electricity 3 Active
US9887072B2 Systems and methods for integrated resputtering in a physical vapor deposition chamber Electricity 3 Active
US11004734B2 Metal-based etch-stop layer Electricity 2 Active
US10867839B2 Patterning methods for semiconductor devices Electricity 2 Active
US10862026B2 Memory device Electricity 2 Active
US10361112B2 High aspect ratio gap fill Electricity 2 Active
US9567668B2 Plasma apparatus, magnetic-field controlling method, and semiconductor manufacturing method Electricity 1 Active
US11322396B2 Etch stop layer for semiconductor devices Electricity 1 Active
US10727045B2 Method for manufacturing a semiconductor device Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.