Integrated circuit chip reliability qualification using a sample-specific expected fail rate
US10539611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2017 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Nov 3, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.