Circuit design verification in a hardware accelerated simulation environment using breakpoints

US10539614B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Rahul Batra · Austin, US
• Debapriya Chatterjee · Austin, US
• John C. Goss · Knightdale, US
• Christopher R. Jones · Santa Monica, US
• Christopher M. Riedl · Austin, US
• John A. Schumann · Austin, US
• Karen Yokum · Austin, US

Key dates

• Filing date: Nov 7, 2017
• Grant date: Jan 21, 2020
• Expiry date: Apr 3, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/33
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.