Patent · US Active

System for managing the wear of an electronic memory

US10540099B2 · kind B2 · utility

1Cited by
1References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 12, 2014
Grant dateJan 21, 2020
Priority date
Expiry dateDec 12, 2034

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2212/7211
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A system including: a first memory including several portions each of several pages, this memory including first and second ports that enable simultaneous access to two pages of distinct portions of the memory; and a control circuit suitable for implementing, via the second port, a method for balancing the wear of the memory, including movements of data within the memory, while authorizing simultaneous user access to the memory contents via the first port.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.