Eliminating redundant stores using a protection designator and a clear designator
US10540178B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2016 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Jan 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for redundant stores includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, a binary translator, and a memory execution unit. The binary translator includes circuitry to identify a first region of the instruction stream including a redundant store, mark a first starting instruction of the first region with a protection designator, mark a first ending instruction of the first region with a clear designator, and store an amended instruction stream with the markings. The memory execution unit includes circuitry to track the first redundant store based on the protection designator and the clear designator to eliminate the first redundant store.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.