Deep neural network processing on hardware accelerators with stacked memory
US10540588B2 · kind B2 · utility
10Cited by
33References
20Claims
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Key dates
| Filing date | Jun 29, 2015 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Aug 13, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for processing on an acceleration component a deep neural network. The method includes configuring the acceleration component to perform forward propagation and backpropagation stages of the deep neural network. The acceleration component includes an acceleration component die and a memory stack disposed in an integrated circuit package. The memory stack has a memory bandwidth greater than about 50 GB/sec and a power efficiency of greater than about 20 MB/sec/mW.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.