DDR memory bus with a reduced data strobe signal preamble timespan
US10541018B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 26, 2017 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Oct 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.