James A. McCall
84Patents
11h-index
75Co-inventors
81Inventor score
Filing activity: Mar 14, 2000 → Oct 2, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6820163B1 | Buffering data transfer between a chipset and memory modules | Physics | 105 | Expired |
| US7542322B2 | Buffered continuous multi-drop clock ring | Emerging Cross-Sectional Technologies | 26 | Expired |
| US6747483B2 | Differential memory interface system | Electricity | 24 | Expired |
| US6366466B1 | Multi-layer printed circuit board with signal traces of varying width | Electricity | 22 | Expired |
| US7772708B2 | Stacking integrated circuit dies | Electricity | 20 | Active |
| US8274308B2 | Method and apparatus for dynamic memory termination | Physics | 17 | Active |
| US6771515B2 | Systems having modules with on die terminations | Electricity | 16 | Expired |
| US8972685B2 | Method, apparatus and system for exchanging communications via a command/address bus | Physics | 14 | Active |
| US9218575B2 | Periodic training for unmatched signal receiver | Physics | 13 | Active |
| US9934842B2 | Multiple rank high bandwidth memory | Emerging Cross-Sectional Technologies | 12 | Active |
| US6674648B2 | Termination cards and systems therefore | Electricity | 12 | Expired |
| US6700457B2 | Impedance compensation for circuit board breakout region | Electricity | 11 | Expired |
| US9153296B2 | Methods and apparatuses for dynamic memory termination | Physics | 11 | Active |
| US6711027B2 | Modules having paths of different impedances | Electricity | 8 | Expired |
| US10146711B2 | Techniques to access or operate a dual in-line memory module via multiple data channels | Emerging Cross-Sectional Technologies | 8 | Active |
| US7246022B2 | Initiation of differential link retraining upon temperature excursion | Physics | 7 | Expired |
| US6717823B2 | Systems having modules with buffer chips | Electricity | 6 | Expired |
| US7676917B2 | Method of manufacturing a circuit board | Emerging Cross-Sectional Technologies | 6 | Active |
| US6711640B1 | Split delay transmission line | Electricity | 5 | Expired |
| US6515555B2 | Memory module with parallel stub traces | Electricity | 5 | Expired |
| US7133962B2 | Circulator chain memory command and address bus topology | Physics | 5 | Expired |
| US7459200B2 | Circuit board design | Emerging Cross-Sectional Technologies | 5 | Expired |
| US7447929B2 | Countering power resonance | Physics | 5 | Active |
| US6597202B1 | Systems with skew control between clock and data signals | Electricity | 5 | Expired |
| US9786353B2 | Reconfigurable clocking architecture | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.