System on integrated chips and methods of forming same
US10541227B2 · kind B2 · utility
43Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.