Contact over active gate structures for advanced integrated circuit structure fabrication
US10541316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2017 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Jul 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0149
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.