Solid state drive controller
US10545695B2 · kind B2 · utility
0Cited by
6References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 16, 2017 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Sep 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may comprise circuitry to adjust between latency and throughput in transferring information through a memory port, wherein the circuitry may be capable of configuring individual partitions or individual sectors as high-throughput storage or low-latency storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.