System-level validation of systems-on-a-chip (SoC)
US10546079B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 6, 2016 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Jun 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. Our methods—which we call Quick Error Detection—Hardware (QED-H)—advantageously quickly detect and fix anomalies (bugs) within SoC hardware components—and in particular customized SoC hardware components that are not necessarily software programmable. Of further advantage, methods according to the present disclosure are compatible with existing Quick Error Detection (QED) techniques while being extensible to target software-programmable components as well. In sharp contrast to prior art methods, method(s) according to the present disclosure represent a new system validation methodology that builds validation checks in both software and hardware components seamlessly and systematically, thus enabling extremely quick error detection and localization for all digital components of the entire SoC advantageously producing productivity and time-to-market gains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.