Resistor network reduction for full-chip simulation of current density
US10546082B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2018 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Apr 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of technology disclosed herein relate to techniques of a full-circuit simulation-based circuit design verification. A simulation is performed to determine current data of parasitic resistors in one or more parasitic resistance networks in power supply circuitry of a circuit design by injecting a current into each one of the one or more parasitic resistance networks. Based on the current data, non-current carrying parasitic resistors are removed from the one or more parasitic resistance network to generate one or more reduced parasitic resistance network. Using the one or more reduced parasitic resistance networks, a full-circuit simulation is performed to obtain current density information. A circuit design verification of the circuit design is then performed based on the current density information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.