Stack package and method of manufacturing the stack package
US10546844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2016 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Jul 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.